PCB Design Review & Optimization
Complete PCB design review covering signal integrity, power delivery, and thermal management
What You Can Do
Get comprehensive PCB design analysis covering power delivery networks, signal integrity, thermal management, and manufacturing constraints. Claude identifies potential issues early and provides specific, actionable optimization recommendations to reduce cost, improve reliability, and accelerate time-to-market. Suitable for designs from initial concept through production-ready layouts.
Features
Analyze impedance profiles, bypass capacitor placement strategies, and power plane designs to optimize PDN performance and reduce noise
Evaluate trace routing, impedance matching, differential pair design, and crosstalk risks to ensure signal quality and timing margins
Plan heat dissipation strategies, optimize thermal via placement, and recommend component positioning for efficient thermal performance
Validate designs against fabrication constraints, review layer stackup efficiency, and identify manufacturability risks at target vendors
Optimize placement of decoupling capacitors, critical components, and thermal management elements to improve performance and manufacturing
Identify design simplifications, layer reduction opportunities, and manufacturing trade-offs to reduce board cost without compromising performance
Assess AC impedance across frequency ranges, identify resonances, and recommend capacitor selection and placement to meet target specs
Example Output
PDN Analysis Summary
- Impedance profile: 2.2mΩ DC → 15mΩ @ 100kHz → 8mΩ @ 1MHz (target: <5mΩ)
- Issue identified: Capacitor placement creates 12mΩ resonance at 500kHz
- Recommendation: Add 4× 10µF ceramic capacitors within 2mm of power pins → reduces loop inductance 40%
Signal Integrity Assessment
- DRAM_CLK @ 250MHz: Impedance mismatch ±8% (spec: ±5%), crosstalk overshoot 110mV (spec: <80mV)
- Routing fix: Length match within 50ps, 0.5mm spacing from parallel signals
- Expected improvement: Timing margin increases from 15% to 25%
Manufacturing & Cost
- Current design: 6 layers, 4mil traces, 8mil vias (25% premium at fab)
- Recommendation: Widen via spacing to 10mil standard in non-critical areas → eliminates premium, zero performance impact
- Estimated savings: 15-20% PCB cost reduction
What's Included
- Comprehensive PDN Assessment: Complete power delivery analysis including impedance profiles, capacitor placement strategy, and layer stackup optimization
- Signal Integrity Evaluation: Detailed evaluation of trace routing, impedance matching, crosstalk analysis, and timing margin assessment
- Thermal Management Plan: Heat dissipation strategy, thermal via placement guidance, and component arrangement recommendations for optimal cooling
- DFM Compliance Review: Manufacturing feasibility assessment against standard fabrication capabilities and cost implications
- Prioritized Optimization Roadmap: Ranked recommendations showing impact, effort, and implementation order for staged design improvements
- Cost-Benefit Analysis: Trade-off analysis for design alternatives showing performance, complexity, and cost implications of each approach
Who It's For
- PCB Design Engineers
- Hardware Design Leads
- Electronics Manufacturing Engineers
- Product Managers (hardware validation)
- Embedded Systems Developers
Best For
- Pre-production PCB design reviews
- Design optimization for cost reduction
- Signal integrity troubleshooting
- Thermal management planning
- Manufacturing feasibility assessment
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