Semiconductor Yield Loss Investigation & Root Cause Analysis
Rapidly investigate semiconductor yield loss and pinpoint process root causes
What You Can Do
You can upload wafer test data, manufacturing logs, and process parameters to quickly identify yield-loss patterns, correlate defects to process conditions, and generate prioritized root cause hypotheses. Claude analyzes multi-dimensional manufacturing data to uncover process bottlenecks, suggest containment actions, and recommend optimization experiments backed by statistical evidence.
Features
Automatically identify spatial and temporal defect clusters across wafer maps, layers, and process batches using statistical clustering and heat map analysis.
Cross-reference yield anomalies with process setpoints (temperature, pressure, duration, materials) to surface process conditions that correlate with loss events.
Synthesize defect data, process logs, and equipment status into ranked root cause hypotheses with evidence scoring and risk assessment.
Apply statistical rigor to validate whether observed yield differences are real or noise, helping you prioritize investigation effort.
Correlate defects across process layers (lithography, etch, deposition) to determine whether root cause is layer-specific or systemic.
Track yield improvement or degradation over time and link trends to equipment maintenance events, process changes, or material lot changes.
Generate containment action plans and design verification experiments to isolate root cause and validate fixes before full-line implementation.
Example Output
Input: Wafer test results (500 wafers), tool parameter logs, and defect classification data.
Output:
- Defect Distribution: 67% metal bridging in M2 layer, clustered in northwest quadrant of wafers processed on Tool_A between 3–5 PM.
- Root Cause Analysis: High probability of CMP over-polish (correlated with Tool_A's slurry feed rate spike on 2026-08-08). Confidence: 84%.
- Recommended Actions: (1) Lower slurry flow rate 15% on Tool_A; (2) Compare CMP film thickness vs. design margin; (3) Run design-of-experiment (DOE) on slurry concentration.
- Verification Plan: Test 50-wafer batch with corrected parameters; expect yield recovery to 98%+ if CMP is root cause.
What's Included
- Yield Loss Investigation Template: Structured framework for collecting data, organizing symptoms, and systematically narrowing root cause search space.
- Defect Classification & Binning Guide: Reference guide for standardizing defect nomenclature and physical binning to align analysis with fab capability and SPC systems.
- Process Correlation Worksheet: Pre-formatted analysis sheet for mapping defect timing/location to process parameter values, material lot codes, and equipment IDs.
- Root Cause Verification Checklist: Systematic checklist to validate hypotheses before implementing fixes, including hypothesis elimination, statistical tests, and DOE design.
- Yield Report Generator: Template for synthesizing findings, recommendations, and next steps into executive-ready briefing slides and engineering documentation.
- Troubleshooting Playbook: Decision tree for common yield-loss scenarios (metal defects, thin film variability, lithography vias, etc.) with typical process culprits.
Who It's For
- Manufacturing Engineers
- Process Engineers
- Yield Engineers
- Quality Assurance Managers
- Production Supervisors
Best For
- Urgent yield loss investigations and containment
- Multi-factor defect root cause isolation
- Process optimization and capability improvement
- Equipment troubleshooting and maintenance planning
- Design-of-experiment planning for process validation
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