Embedded System Architecture Review & Optimization
Review and optimize embedded system architectures for performance and reliability
What You Can Do
You get a comprehensive analysis of your embedded system design covering memory footprint, power consumption, real-time performance, and hardware-software tradeoffs. Claude identifies architectural bottlenecks, suggests optimization strategies, and validates your design against reliability and performance requirements specific to embedded constraints.
Features
Analyze RAM usage, flash allocation, and heap fragmentation patterns to fit tight microcontroller constraints
Identify power-hungry components and sleeping modes, with optimization strategies for battery-dependent systems
Evaluate interrupt handling, task scheduling, and latency requirements to ensure deterministic behavior
Compare CPU vs. hardware accelerator approaches and identify optimal peripheral usage for your workload
Review bootloader design, update mechanisms, and firmware modularity for maintainability and OTA safety
Analyze race conditions, deadlock risks, and suggest thread-safe patterns for multi-core or RTOS environments
Validate SPI/I2C/UART/CAN configurations and clock domain interactions for signal integrity
Review authentication, encryption implementation, and attack surface relative to embedded threat models
Example Output
Example 1: Memory Optimization Report
### Current State
- RAM usage: 28KB / 32KB (87%)
- Heap fragmentation: 6% wasted
- Stack peak: 4.2KB
### Issues Found
- Global buffers in multiple compilation units (4KB redundancy)
- String literals not pooled (1.8KB savings available)
- DMA buffer descriptors allocated on stack (unsafe)
### Recommendations
- Consolidate buffers into single module [PRIORITY: HIGH]
- Use const data section for strings [SAVINGS: ~1.8KB]
- Move DMA descriptors to static memory [IMPACT: Stack safety]
Example 2: Power Profile Analysis
### Power Breakdown (100 mA avg current)
- MCU active: 45 mA (45%)
- Cellular modem: 38 mA (38%)
- Sensors: 12 mA (12%)
- Peripherals: 5 mA (5%)
### Optimization Path
1. Enable adaptive CPU frequency scaling → -8 mA
2. Implement modem sleep between transmissions → -25 mA (65% reduction)
3. Reduce sensor polling from 1s to 10s → -10 mA
### Result: ~60 mA sustained (40% improvement)
Example 3: Real-Time Latency Audit
### Critical Path Analysis
- Interrupt to ISR entry: 12 μs ✓
- ISR execution (worst-case): 145 μs ✗ (exceeds 100 μs deadline)
- Task preemption latency: 8 μs ✓
### Issues
- ADC ISR holds spinlock too long
- printf() call in high-priority interrupt context
### Fix
- Move formatting to task-level handler
- Reduce lock time to <30 μs
What's Included
- SKILL.md: Complete embedded architecture review workflow with templates for design documentation and optimization planning
- Review checklist: Comprehensive rubric covering memory, power, real-time, security, and hardware integration
- Architecture diagram template: Ready-to-fill block diagram format for MCU, peripherals, and power domains
- Optimization strategy worksheet: Structured template for prioritizing changes by impact vs. effort
- Benchmark comparison table: Before/after metrics template for validating improvements
Who It's For
- Embedded systems engineers designing microcontroller or IoT firmware
- Hardware engineers validating firmware efficiency against constraints
- Technical leads optimizing existing embedded products for battery life or cost reduction
- Systems architects designing multi-MCU or edge device deployments
- Product managers evaluating feasibility of features within hardware limits
Best For
- Reviewing microcontroller firmware architecture before implementation
- Diagnosing memory or power consumption issues in deployed systems
- Optimizing real-time performance for latency-critical applications
- Evaluating hardware-software tradeoffs for new product iterations
- Planning firmware refactors to meet evolving power or memory budgets
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